Abstract: Nand Flash has been widely used in modern digital products due to its superior features and higher cost performance. Integrating the Nand Flash controller into a system-on-a-chip has become a trend. This paper presents a Nand Flash controller implementation in a system-on-a-chip (SoC) chip based on the ARM7TDMI CPU CORE. Through the direct memory access (DMA) data transmission method, the data transmission rate of Nand Flash has been improved to meet the design requirements of practical applications. The design method has passed the RTL level verification, FGPA verification, and has been implemented on the actual chip demonstration prototype.
This article refers to the address: http://
Keywords: system on chip; Nand Flash; direct memory access
1 Introduction
Flash is widely used in handheld devices such as digital cameras, mobile phones, personal digital assistants (PDAs), PDAs, and MP3 players because of its non-volatility and erasability. Since Toshiba’s Nand Flash architecture was released in 1989, Nand Flash has a smaller footprint, faster write and erase speeds, more erasable times, and lesser cost per second than Nor Flash. The price of the bit has been rapidly developed. The high-capacity Nand Flash is especially suitable for storage of large data volumes in digital devices, which can reduce costs and improve performance.
ARM7TDMI is a 32-bit embedded RISC low-end processor core widely used in the world. Integrating the Nand Flash controller in the SoC (System on Chip) chip based on the ARM7TDMI core will greatly expand the application range of the chip, reduce the cost of the chip, and enhance the product. performance. However, the use of Nand-type flash memory is quite difficult in terms of hardware design and software control compared to Nor-type flash memory, and it is worth further exploration and research in technology.
2 Nand Flash's structural features limit its reading and writing
The Nand Flash selected by the author is Toshiba TC58512FT (see Figure 1). The Nand Flash of this model consists of 528 bytes to form a page. 32 pages form a block, and 4096 blocks make up the entire flash memory. The first 512 bytes in each page is used to store data, and the next 16 bytes is used to store the ECC data check code, called the OOB (Out of Bank) area. Reading and writing to Nand Flash is in units of pages, while erasing is done in blocks, similar to the way the hard disk is used in storage organization. The amount of data must be an integer multiple of the page size when reading and writing. This is completely different from the way NorFlash can read and write randomly, but for the reading and writing of large amounts of data, this is the advantage of Nand Flash. reflect.
Based on the special organizational structure of Nand Flash, a transmission method suitable for reading and writing according to the unit size is considered in design, that is, DMA (Direct Memory Access) is used to configure the DMA channel for each read and write, so that a whole page is transmitted. The amount of data. During the transfer, the DMA module occupies the bus and releases the bus after the transfer is complete. Because DMA data transmission efficiency is higher than CPU CORE by directly sending instructions to Flash and then reading and writing Nand Flash I / O port data, so this design is conducive to improve read and write speed, thereby improving the performance of Nand Flash controller.
Figure 1 TC58512FT 512M-bit Nand Fla sh organization chart
3 Nand Flash controller structure and workflow
As shown in Figure 2, the Nand Flash controller and DMA controller (DMAC) are the master modules on the AMBA (ARM Bus Standard) high-speed bus AHB, and all contain AMBA-compliant bus interface modules to interact with them.
Figure 2 Nand Flash controller and DMA module organization chart
The Nand Flash controller includes a bus interface module, a state control module that controls state machine conversion, a register set to buffer data, send and receive commands and status words, an ECC algorithm programming/decoder module that provides ECC check error correction codes, and direct control. Interface module for "naked" Nand Flash body.
The bus interface module is responsible for accepting instructions sent by the ARM CORE (CPU core), sending and receiving data to the corresponding data registers and instruction registers, and returning the contents of the status register to CORE. The register set is responsible for the control of the entire flash controller, including instructions, status, data, error address registers, etc., is the core of the controller. The ECC algorithm programming/decoder module provides a verification function that provides error correction information.
The state control module provides a rollover of 21 types of Nand Flash states including a command word transmission status group, an address transmission status group, a read status group, and a write status group, for issuing a Nand flash read/write control signal. The interface module directly connected to Nand Flash provides the corresponding level state required for Nand Flash body operating voltage, enable and action, such as the read timing requirement shown in Figure 3. This module is controlled by the state machine control module. The controller's level control simplifies software operation, and the driver software no longer has to configure cumbersome control levels in accordance with read and write timing.
Figure 3 Nand Flash read timing diagram to read a page of data blocks from Nand Flash to the memory first address 0x30000000 as an example to analyze the working process of the controller. First, the ARM CORE sends an instruction to configure a DMA channel, configures the DMA source address register as the Nand Flash data register address, the target address register is 0x30000000, configures the DMA_Control, DMA_Config registers, and sets the Burst transfer size of the DMA transfer. Data width, total data volume (should be page size 512bytes), etc., and enable the channel to wait for the request signal sent by other master modules. Second, configure the Nand Flash controller's address register (specify which page to read from Flash) Data) and Nand _ Config register; Finally, the read command word 0x80000000 is sent to send a transfer request signal to the DMAC. Once the request is accepted, the DMAC takes up the AHB bus and begins high speed block transfers.
The Nand Flash controller continuously reads 32-bit data from the Nand Flash body through the 8-bit I/O port and places it into the Flash data register. The DMA reads the data from the data register into the DMA data buffer fifo. When the amount of data in fifo reaches the set Burst size, it is shipped to the specified memory address, the DMA data counter is decremented by 1, and then the data is read from the Nand Flash data register, and the DMA data buffer is filled until the counter reaches 0. The number of transfers is preset, and the DMA releases the bus, thus completing the reading of one page of data. If you continue to read, you need to re-initiate the command by CORE to configure the DMA and Nand Flash registers. Of course, DMAC and Nand Flash must be synchronized with the same HCLK to keep the actions between modules consistent. When writing data to Nand Flash, the control process is roughly the same, and the data flow is in the opposite direction.
Compared with the way of directly sending command words to NandFlash by CORE and then reading and writing data directly from the I/O port, the efficiency of transmission by DMA is obviously high. Especially in the case of continuously reading large quantities of data, the advantages of this way of working can be better reflected. In actual product applications (such as digital photo access), the amount of read and write data is generally thousands of times the page size, so this design helps to improve the usability. For the sake of SOC chip area and power consumption, some functions of the general controller are simplified, such as identifying the chip model. Because the specific NandFlash model is ok in the specific application, just skip this step in the driver development and fill in the specific known information.
4 module verification and application development
4. 1 Module Verification The module has passed the register level (RTL) simulation, post-simulation verification and verification on the ARM FPGA development board on the SUN server with ARM7TDMI CORE, and got the specific on the actual chip demonstration prototype. Application verification. Write a test vector (Testbench) for VCS verification on the SUN server. See Figure 4 for a screenshot. The signal content in the figure is the system bus signal.
Figure 4 SUNSERVER Nand Fla sh controller RTL signal simulation timing diagram On the ARM FPGA development board, a screenshot of the verification program using the ADS development kit and ARM Multi-ICE is shown in Figure 5.
Figure 5 ARM ADS development system interface memory area shows the test program written in C language. The general process is to erase the data of a block address of Flash first, then write a certain amount of data to the address, and then read it. In the memory area, you can see the contents of SDRAM or SRAM on the development board. The content should be written and written. The data entered are completely consistent, and if they are consistent, the reading and writing are successful. The use of the ADS Development Kit is not described here.
4. 2 About the bootloader and booting the system from Nand Flash Since the Nand Flash manufacturer guarantees that the first block is the available block, the bootloader can be placed in the first page of Flash to implement NandFlash. Start the system. Set the external jumper and select the system to boot from Nand Flash. When the system with the chip is powered on, the DMAC occupies the system bus by default, and automatically transfers data from the first page of Nand Flash (that is, the bootloader program burned in advance) to the ESRAM in the chip, and starts from the ESRAM. Execute the bootloader statement.
This piece of code is written in assembly language and the main work done is:
(1) Initialization of off-chip memory controller (EMI) to make the memory readable and writable;
(2) Handle the Kernel code of the operating system stored in Nand Flash to a larger memory (usually SDRAM), and then set the remap register so that the memory address of Kernel points to zero, so that the interrupt vector table must be stored from the zero address. Requirements
(3) Finally set the program counter (PC) to zero, start running from the Kernel code, and really start the operating system.
The above application has been specifically implemented in the demonstration prototype of the actual chip, and achieved the intended design goal.
5 Conclusion
This paper presents the implementation of the Nand Flash controller in a system-on-chip (SoC) chip design, and introduces the verification process and application. The design has been confirmed in the application of the prototype prototype of the finished chip, and has considerable application value, achieving the expected design effect.
The typical Electrical Wire harnesses that ETOP supplies include dozens of wires and sometimes hundreds of different components and terminations. Our engineering staff is well versed in the design and construction of wire harnesses and is available to assist in the development of the most efficient wiring harness to meet your demands. A basic Wire Harness may include as few as three discreet components, while the more classic harnesses include many more wires and other passive, and potentially active, components.
Electrical Wiring Harness, terminal wiring, wire assembling,bullet terminals, lead wire assembly
ETOP WIREHARNESS LIMITED , https://www.oemmoldedcables.com