Abstract: ApplicaTIon Note 304 provides a logical diagram of the interface of the Dallas Semiconductor / Maxim DS2151 T1 single chip transceiver (SCT) and DS2153 E1 SCT to the AT & T T7270.
Notes: CMS = 0 in the T7270. Gate # 1 is used to condiTIon the frame sync to meet the TIming requirements of the T7270. In the master, no elasTIc stores are enabled; in the slave, both the receive and the transmit side elastic stores are enabled. A "loop-timed" application is shown. In the master, RCHBLK is programmed to go high during the last channel. Timing is shown below:
Notes: CMS = 0 in the T7270. Gate # 1 is used to condiTIon the frame sync to meet the TIming requirements of the T7270. In the master, no elasTIc stores are enabled; in the slave, both the receive and the transmit side elastic stores are enabled. A "loop-timed" application is shown. In the master, RCHBLK is programmed to go high during the last channel. Timing is shown below:
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